Mentor Graphics Catapult High-Level Synthesis PLD设计与仿真

Catapult’s advanced power optimizations automatically provide significant reductions in dynamic power consumption. The highly-interactive Catapult workflow provides full visibility and control of the synthesis process, enabling designers to rapidly converge upon the best implementation for power, performance, and area.

CATAPULT HLS PLATFORM：

• C/C++/SystemC Synthesis HLS

Lets designers use industry standard ANSI C++ or SystemC to describe functional intent at the ESL level. From these high-level descriptions, Catapult automatically generates production-quality RTL to dramatically shorten both design and verification in hardware design flows.

• HLS Verification

HLS Verification with the Catapult Platform has three categories:

1. Automatic/formal checking of users HLS targeted C++/SystemC code finding errors before synthesis.
2. Simulation based verification comparing functionality of users C++/SystemC source with generated RTL including metrics such as coverage and assertions.
3. Formal verification of equivalence of the users C++/SystemC code with the generated RTL from synthesis

• Low-Power HLS

The industry’s first HLS tool that adds power as an optimization goal. By leveraging Calypto’s existing best in class power analysis and optimization technology, Catapult Low-Power provides a closed-loop optimization across power, performance and area to address the challenges of power-aware design.