Aldec China Riviera-PRO PLD设计与仿真

Top Features and Benefits：

1. High Performance Simulation

• Extensive simulation optimization algorithms to achieve the highest performance in VHDL, Verilog/SystemVerilog, SystemC, and mixed-language simulations
• The industry-leading capacity and simulation performance enable high regression throughput for developing the most complex systems
• Support for the latest Verification Libraries, including Universal Verification Methodology (UVM)

2. Advanced Debugging

• Integrated multi-language debug environment enables automating time-consuming design analysis tasks and fixing bugs quickly
• UVM Toolbox, UVM graph, Class Viewer, Transaction streams and data to allow visual mapping and debugging of designs based on OVM/UVM class libraries
• Built-in debugging tools provide code tracing, waveform, dataflow, FSM window, coverage, assertion, and memory visualization capabilities
• Comprehensive Assertion-Based Verification (SVA and PSL) for increased design observability and decreased debug time
• Advanced Code and Functional Coverage capabilities and Coverage analysis tools for fast metric-based verification closure
• Efficient verification flow with user-defined test plan linking with coverage database
• Plot viewer and Image viewer tools for visual representation of large arrays of data.

3. Industry’s Best ROI

• Riviera-PRO enables Aldec customers to deliver innovative products at a lower cost in shorter time
• Features partnerships and integrations necessary to build complete design and verification flows
• Deployment of any Aldec solution is accompanied by comprehensive training and support