Mentor Graphics PowerPro 开发语言/工具

PowerPro

Throughout the development process, the power exploration flow provides guidance on where power is wasted and how to reduce it. Designers can also perform “what-if” analysis, interactively assessing the impact on power of potential design transformations.

Finally, as the RTL nears completion, designers can leverage the optimization flow to automatically generate new, power-optimized RTL, which is formally verified using PowerPro’s SLEC technology, saving hours/days of verification time. Using patented deep sequential analysis technology, PowerPro sweeps the RTL design to find the most advanced logic conditions possible to shut off redundant sections of a chip.

Using PowerPro, designers achieve maximum power reduction for their SoC.

POWERPRO RTL LOW-POWER PLATFORM：

• Power Estimation

PowerPro provides the industry’s most accurate register-transfer level (RTL) power estimation solution. This dramatic advantage in accuracy over other solutions is made possible by PowerPro’s new and unique technology developed and optimized for FinFET designs..

• Guided Power Reduction

PowerPro’s power reduction features are fully integrated within the RTL power estimation flow. Used throughout the RTL design cycle, PowerPro interactively guides designers to achieve the lowest power implementations.

• Automatic Power Reduction

Low-Power RTL and all of the optimizations performed by PowerPro are comprehensively verified by the SLEC Pro formal verification engine.