Mentor Graphics Oasys-RTL IC设计

Oasys-RTL, formerly called RealTime Designer, provides better quality of results by enabling physical accuracy, floorplanning, and fast optimization iterations to get to design closure on time.

Oasys-RTL addresses the need for higher capacity, faster runtimes, improved QoR, and physical awareness by optimizing at a higher level of abstraction along with offering an integrated floorplanning and placement capabilities.

FEATURES AND BENEFITS:

• Physically-aware RTL synthesis based on patented “PlaceFirst” technology
• Optimization at RTL level for the best quality of results
• Higher level of abstraction to handle 100+ million gates
• Runtimes up to 10x faster than traditional RTL synthesis
• Integrated cockpit for advanced cross probing between logical, physical, timing and other views
• Integrated links for formal equivalency checking
• Parallel design space exploration of PPA metrics

Summary

Oasys-RTL represents a paradigm shift in the RTL synthesis domain with its unique physical RTL synthesis engine. Oasys-RTLdelivers up to 10x faster synthesis run times compared to traditional synthesis tools while also delivering optimal PPA metrics. Its unique scalable architecture provides 100+ million gate design capacity to tackle the growing design sizes with ease with a compact memory footprint.